1. Field
Exemplary embodiments of the present invention relate generally to a semiconductor design technology and, more particularly, to a charge pump circuit of a semiconductor memory device and an internal voltage generation circuit including the same.
2. Description of the Related Art
Semiconductor memory devices generate internal voltages having various levels using an external voltage, and the internal voltages are used for various internal operations of the semiconductor memory devices.
Existing methods for generating internal voltages using an external voltage are largely divided into two categories. According to a first category method, an internal voltage lower than an external voltage may be generated by down-converting the external voltage to a lower potential. According to a second category method, an internal voltage may be generated that is higher than an external voltage or lower than a ground voltage by charge-pumping the external voltage.
A high voltage VPP and a back bias voltage VBB are widely used as internal voltages generated through charge-pumping. The high voltage VPP is generated in order for the gate of a cell transistor (or word line) to have a higher potential than a power supply voltage VCC as an external voltage, thereby preventing a loss of cell data and accessing a memory cell. The back bias voltage VBB is generated in order for the bulk of a cell transistor to have a lower potential than a ground voltage VSS as an external voltage, thereby preventing a loss of cell data.
FIG. 1 is a diagram illustrating a conventional charge pump circuit 10.
Referring to FIG. 1, the charge pump circuit 10 includes a charge pump unit 12, an output capacitor C0 and a switch SW.
The charge pump unit 12 pumps an input voltage to an output voltage VPASSPMP which is boosted to a level required by a load circuit 20. The charge pump unit 12 may include a plurality of switches (not illustrated) which are turned on/off based on first and second clocks CLK1 and CLK2 which are complementary in phase. The charge pump unit 12 may charge an output capacitor C0 with charge of a specific node of the switches or discharge the output capacitor C0, and thus acquire the boosted output voltage VPASSPMP at an output terminal OUT_ND.
That is, the charge pump circuit 10 generates the output voltage VPASSPMP at a high voltage level by boosting the input voltage, and uses the output capacitor C0 to retain the boosted output voltage VPASSPMP at a predetermined level. The load circuit 20 coupled to the output terminal OUT_ND of the charge pump circuit 10 may receive a voltage and current from the charge pump circuit 10.
The operation of the above-described charge pump circuit 10 will be described as follows. At the beginning, the charge pump circuit 10 opens the switch SW, and performs a charge pump operation to charge the output capacitor C0 with the boosted output voltage VPASSPMP. Then, when the output voltage VPASSPMP reaches a target voltage, the charge pump circuit 10 may close the switch SW. The output voltage VPASSPMP of the charge pump circuit 10 is supplied to an input terminal INIT_ND of the load circuit 20.
At this time, when the output voltage VPASSPMP of the charge pump circuit 10 is supplied to the input terminal INIT_ND of the load circuit 20, a charge sharing operation is performed. At the moment that the output terminal OUT_ND of the charge pump circuit 10 and the input terminal INIT_ND of the load circuit 20 have the same capacitance during the charge sharing operation, the charge pump circuit 10 may provide a voltage having the intermediate level of the output voltage VPASSPMP to the load circuit 20.
In the charge pump circuit 10, the capacitance (or size) of the output capacitor C0 may be determined in consideration of the voltage/current supply ability of the charge pump circuit 10, and current amount and voltage stability (ripple) required by the load circuit 20.
That is, when the output capacitor C0 has a high capacitance, a voltage ripple caused by the pumping operation may be reduced, and the voltage retention ability of charge pump circuit 10 may be improved even though the load circuit 20 momentarily uses current. However, for retaining the capacitance, the output capacitor C0 requires a large amount of charge at the initial stage. Furthermore, since the charge pump circuit 10 considers the output capacitor C0 as a load, the charge pump circuit 10 requires a larger amount of time to recover the voltage of the output terminal OUT_ND when the voltage of the output terminal OUT_ND is lowered. On the other hand, when the output capacitor C0 has a small capacitance, the voltage of the output terminal OUT_ND may be recovered within a short time, even though the voltage of the output terminal OUT_ND is lowered. However, a voltage ripple caused by the pumping operation may be increased, and a voltage variation may occur due to momentary current consumption.
Therefore, there have been difficulties in determining the capacitance of the output capacitor C0 of the charge pump circuit 10.